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1 Ergebnisse
1
A 2–20 Gbps Clock and Data Recovery Based on Phase Interpol..:
Chen, Yinghao
;
Chen, Yingmei
;
Fan, Wentian
...
Circuits, Systems, and Signal Processing. 43 (2023) 1 - p. 318-330 , 2023
Link:
https://doi.org/10.1007/s00034-023-02473-5
RT Journal T1 <Title>A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1007_s00034-023-02473-5&Exemplar=1&LAN=DE A1 Chen, Yinghao A1 Chen, Yingmei A1 Fan, Wentian A1 Zhao, Qingyi A1 Zhu, En A1 Hu, Zhengfei PB Springer Science and Business Media LLC YR 2023 SN 0278-081X SN 1531-5878 JF Circuits, Systems, and Signal Processing VO 43 IS 1 SP 318 OP 330 LK http://dx.doi.org/https://doi.org/10.1007/s00034-023-02473-5 DO https://doi.org/10.1007/s00034-023-02473-5 SF ELIB - SuUB Bremen
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