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1 Ergebnisse
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Architecture optimization for energy-efficient resolution-s..:
Bos, Thomas
;
Badami, Komail
;
Dehaene, Wim
.
Analog Integrated Circuits and Signal Processing. 97 (2018) 3 - p. 437-448 , 2018
Link:
https://doi.org/10.1007/s10470-018-1235-0
RT Journal T1 <Title>Architecture optimization for energy-efficient resolution-scalable 8–12-bit SAR ADCs</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1007_s10470-018-1235-0&Exemplar=1&LAN=DE A1 Bos, Thomas A1 Badami, Komail A1 Dehaene, Wim A1 Verhelst, Marian PB Springer Science and Business Media LLC YR 2018 SN 0925-1030 SN 1573-1979 JF Analog Integrated Circuits and Signal Processing VO 97 IS 3 SP 437 OP 448 LK http://dx.doi.org/https://doi.org/10.1007/s10470-018-1235-0 DO https://doi.org/10.1007/s10470-018-1235-0 SF ELIB - SuUB Bremen
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