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VLSI implementation of residue number system based efficien..:
Ananthalakshmi, A. V.
;
Rajagopalan, P.
International Journal of Information Technology. 11 (2019) 4 - p. 829-840 , 2019
Link:
https://doi.org/10.1007/s41870-019-00297-8
RT Journal T1 <Title>VLSI implementation of residue number system based efficient digital signal processor architecture for wireless sensor nodes</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1007_s41870-019-00297-8&Exemplar=1&LAN=DE A1 Ananthalakshmi, A. V. A1 Rajagopalan, P. PB Springer Science and Business Media LLC YR 2019 SN 2511-2104 SN 2511-2112 JF International Journal of Information Technology VO 11 IS 4 SP 829 OP 840 LK http://dx.doi.org/https://doi.org/10.1007/s41870-019-00297-8 DO https://doi.org/10.1007/s41870-019-00297-8 SF ELIB - SuUB Bremen
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