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1 Ergebnisse
1
Digital Test Architectures:
, In:
System-on-Chip Test Architectures
,
Wang, Laung-Terng (L.-T.)
- p. 41-121 , 2008
Link:
https://doi.org/10.1016/b978-012373973-5.50007-3
RT T1 <cTitle>System-on-Chip Test Architectures</cTitle>: T1 <Title>Digital Test Architectures</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1016_b978-012373973-5.50007-3&Exemplar=1&LAN=DE A1 Wang, Laung-Terng (L.-T.) PB Elsevier YR 2008 SP 41 OP 121 LK http://dx.doi.org/https://doi.org/10.1016/b978-012373973-5.50007-3 DO https://doi.org/10.1016/b978-012373973-5.50007-3 SF ELIB - SuUB Bremen
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