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A High Parallelism Hardware Architecture Design of the H.26..:
Lunarejo, José Luis Santos
;
Cárdenas, Carlos Silva
Procedia Technology. 17 (2014) - p. 728-735 , 2014
Link:
https://doi.org/10.1016/j.protcy.2014.10.273
RT Journal T1
A High Parallelism Hardware Architecture Design of the H.264/AVC Integer Motion Estimation for Applications in Real-time DTTV Transmissions
UL https://suche.suub.uni-bremen.de/peid=cr-10.1016_j.protcy.2014.10.273&Exemplar=1&LAN=DE A1 Lunarejo, José Luis Santos A1 Cárdenas, Carlos Silva PB Elsevier BV YR 2014 SN 2212-0173 JF Procedia Technology VO 17 SP 728 OP 735 LK http://dx.doi.org/https://doi.org/10.1016/j.protcy.2014.10.273 DO https://doi.org/10.1016/j.protcy.2014.10.273 SF ELIB - SuUB Bremen
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