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1 Ergebnisse
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FPGA implementation of hardware architecture with AES encry..:
Arul Murugan, C.
;
Karthigaikumar, P.
;
Sathya Priya, Sridevi
Automatika. 61 (2020) 4 - p. 682-693 , 2020
Link:
https://doi.org/10.1080/00051144.2020.1816388
RT Journal T1
FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
UL https://suche.suub.uni-bremen.de/peid=cr-10.1080_00051144.2020.1816388&Exemplar=1&LAN=DE A1 Arul Murugan, C. A1 Karthigaikumar, P. A1 Sathya Priya, Sridevi PB Informa UK Limited YR 2020 SN 0005-1144 SN 1848-3380 JF Automatika VO 61 IS 4 SP 682 OP 693 LK http://dx.doi.org/https://doi.org/10.1080/00051144.2020.1816388 DO https://doi.org/10.1080/00051144.2020.1816388 SF ELIB - SuUB Bremen
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