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High-speed and parallel approach for decoding of binary BCH..:
Kumar, H. Prashantha
;
Sripati, U.
;
Shetty, K. Rajesh
International Journal of Electronics. 99 (2012) 5 - p. 683-693 , 2012
Link:
https://doi.org/10.1080/00207217.2011.643498
RT Journal T1
High-speed and parallel approach for decoding of binary BCH codes with application to Flash memory devices
UL https://suche.suub.uni-bremen.de/peid=cr-10.1080_00207217.2011.643498&Exemplar=1&LAN=DE A1 Kumar, H. Prashantha A1 Sripati, U. A1 Shetty, K. Rajesh PB Informa UK Limited YR 2012 SN 0020-7217 SN 1362-3060 JF International Journal of Electronics VO 99 IS 5 SP 683 OP 693 LK http://dx.doi.org/https://doi.org/10.1080/00207217.2011.643498 DO https://doi.org/10.1080/00207217.2011.643498 SF ELIB - SuUB Bremen
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