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1 Ergebnisse
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High data-rate readout logic design of a 512 × 1024 pixel a..:
Wei, X.
;
Wei, W.
;
Wu, T.
...
Journal of Instrumentation. 14 (2019) 12 - p. C12012-C12012 , 2019
Link:
https://doi.org/10.1088/1748-0221/14/12/c12012
RT Journal T1
High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector
UL https://suche.suub.uni-bremen.de/peid=cr-10.1088_1748-0221_14_12_c12012&Exemplar=1&LAN=DE A1 Wei, X. A1 Wei, W. A1 Wu, T. A1 Zhang, Y. A1 Li, X. A1 Zhang, L. A1 Lu, W. A1 Liang, Z. A1 Dong, J. A1 Li, L. A1 Wang, J. A1 Zheng, R. A1 Casanova, R. A1 Grinstein, S. A1 Hu, Y. A1 Costa, J. Guimaraes da PB IOP Publishing YR 2019 SN 1748-0221 JF Journal of Instrumentation VO 14 IS 12 SP C12012 OP C12012 LK http://dx.doi.org/https://doi.org/10.1088/1748-0221/14/12/c12012 DO https://doi.org/10.1088/1748-0221/14/12/c12012 SF ELIB - SuUB Bremen
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