I agree that this site is using cookies. You can find further informations here.
X
Merkliste 
 1 Ergebnisse 
 
1

C-testable design techniques for iterative logic arrays:

Shyue-Kung Lu ; Jen-Chuan Wang ; Cheng-Wen Wu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  3 (1995)  1 - p. 146-152 , 1995
Link: https://doi.org/10.1109/92.365462