I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
Interleaving buffer insertion and transistor sizing into a ..:
Yanbin Jiang
;
Sapatnekar, S.S.
;
Bamji, C.
.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 6 (1998) 4 - p. 625-633 , 1998
Link:
https://doi.org/10.1109/92.736136
RT Journal T1 <Title>Interleaving buffer insertion and transistor sizing into a single optimization</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_92.736136&Exemplar=1&LAN=DE A1 Yanbin Jiang A1 Sapatnekar, S.S. A1 Bamji, C. A1 Juho Kim PB Institute of Electrical and Electronics Engineers (IEEE) YR 1998 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 6 IS 4 SP 625 OP 633 LK http://dx.doi.org/https://doi.org/10.1109/92.736136 DO https://doi.org/10.1109/92.736136 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)
