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FPGA Acceleration of Pre-Alignment Filters for Short Read M..:
Castells-Rufas, David
;
Marco-Sola, Santiago
;
Moure, Juan Carlos
..
IEEE Access. 10 (2022) - p. 22079-22100 , 2022
Link:
https://doi.org/10.1109/access.2022.3153032
RT Journal T1
FPGA Acceleration of Pre-Alignment Filters for Short Read Mapping With HLS
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_access.2022.3153032&Exemplar=1&LAN=DE A1 Castells-Rufas, David A1 Marco-Sola, Santiago A1 Moure, Juan Carlos A1 Aguado, Quim A1 Espinosa, Antonio PB Institute of Electrical and Electronics Engineers (IEEE) YR 2022 SN 2169-3536 JF IEEE Access VO 10 SP 22079 OP 22100 LK http://dx.doi.org/https://doi.org/10.1109/access.2022.3153032 DO https://doi.org/10.1109/access.2022.3153032 SF ELIB - SuUB Bremen
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