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Evaluation of a 100-nm Gate Length E-Mode InAs High Electro..:
Yao, Jing-Neng
;
Lin, Yueh-Chin
;
Hsu, Heng-Tung
...
IEEE Journal of the Electron Devices Society. 6 (2018) - p. 797-802 , 2018
Link:
https://doi.org/10.1109/jeds.2018.2853547
RT Journal T1 <Title>Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_jeds.2018.2853547&Exemplar=1&LAN=DE A1 Yao, Jing-Neng A1 Lin, Yueh-Chin A1 Hsu, Heng-Tung A1 Yang, Kai-Chun A1 Hsu, Hisang-Hua A1 Sze, Simon M. A1 Chang, Edward Yi PB Institute of Electrical and Electronics Engineers (IEEE) YR 2018 SN 2168-6734 JF IEEE Journal of the Electron Devices Society VO 6 SP 797 OP 802 LK http://dx.doi.org/https://doi.org/10.1109/jeds.2018.2853547 DO https://doi.org/10.1109/jeds.2018.2853547 SF ELIB - SuUB Bremen
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