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1 Ergebnisse
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A Compute-in-Memory Hardware Accelerator Design With Back-E..:
Luo, Yandong
;
Dutta, Sourav
;
Kaul, Ankit
...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 12 (2022) 2 - p. 445-457 , 2022
Link:
https://doi.org/10.1109/jetcas.2022.3177577
RT Journal T1 <Title>A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_jetcas.2022.3177577&Exemplar=1&LAN=DE A1 Luo, Yandong A1 Dutta, Sourav A1 Kaul, Ankit A1 Lim, Sung Kyu A1 Bakir, Muhannad A1 Datta, Suman A1 Yu, Shimeng PB Institute of Electrical and Electronics Engineers (IEEE) YR 2022 SN 2156-3357 SN 2156-3365 JF IEEE Journal on Emerging and Selected Topics in Circuits and Systems VO 12 IS 2 SP 445 OP 457 LK http://dx.doi.org/https://doi.org/10.1109/jetcas.2022.3177577 DO https://doi.org/10.1109/jetcas.2022.3177577 SF ELIB - SuUB Bremen
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