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Reduced bit low power VLSI architectures for motion estimat..:
Agha, Shahrukh
;
Khan, Shahid
;
Malik, Shahzad
.
Journal of Systems Engineering and Electronics. 24 (2013) 3 - p. 382-399 , 2013
Link:
https://doi.org/10.1109/jsee.2013.00047
RT Journal T1 <Title>Reduced bit low power VLSI architectures for motion estimation</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_jsee.2013.00047&Exemplar=1&LAN=DE A1 Agha, Shahrukh A1 Khan, Shahid A1 Malik, Shahzad A1 Riaz, Raja PB Institute of Electrical and Electronics Engineers (IEEE) YR 2013 SN 1004-4132 JF Journal of Systems Engineering and Electronics VO 24 IS 3 SP 382 OP 399 LK http://dx.doi.org/https://doi.org/10.1109/jsee.2013.00047 DO https://doi.org/10.1109/jsee.2013.00047 SF ELIB - SuUB Bremen
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