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A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus De..:

Ryu, Yesin ; Ahn, Sung-Gi ; Lee, Jae Hoon...
IEEE Journal of Solid-State Circuits. 58 (2023) 4 - p. 1051-1061 , 2023

Link: https://doi.org/10.1109/jssc.2022.3232096

RT Journal
T1 <Title>A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features</Title>

UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_jssc.2022.3232096&Exemplar=1&LAN=DE
				
A1 Ryu, Yesin
A1 Ahn, Sung-Gi
A1 Lee, Jae Hoon
A1 Park, Jaewon
A1 Kim, Yong Ki
A1 Kim, Hyochang
A1 Song, Yeong Geol
A1 Cho, Han-Won
A1 Cho, Sunghye
A1 Song, Seung Ho
A1 Lee, Haesuk
A1 Shin, Useung
A1 Ahn, Jonghyun
A1 Ryu, Je-Min
A1 Lee, Sukhan
A1 Lim, Kyoung-Hwan
A1 Lee, Jungyu
A1 Park, Jeong Hoan
A1 Jeong, Jae-Seung
A1 Joo, Sunghwan
A1 Cho, Dajung
A1 Kim, So Young
A1 Lee, Minsu
A1 Kim, Hyunho
A1 Kim, Minhwan
A1 Kim, Jae-San
A1 Kim, Jinah
A1 Kang, Hyun Gil
A1 Lee, Myung-Kyu
A1 Kim, Sung-Rae
PB Institute of Electrical and Electronics Engineers (IEEE)
YR 2023
SN 0018-9200
SN 1558-173X
JF IEEE Journal of Solid-State Circuits
VO 58
IS 4
SP 1051
OP 1061
LK http://dx.doi.org/https://doi.org/10.1109/jssc.2022.3232096
DO https://doi.org/10.1109/jssc.2022.3232096
SF ELIB - SuUB Bremen

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