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1 Ergebnisse
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A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DT..:
Ye, Zonglin
;
Geng, Xinlin
;
Xiao, Yao
..
IEEE Journal of Solid-State Circuits. 59 (2024) 3 - p. 677-689 , 2024
Link:
https://doi.org/10.1109/jssc.2023.3339679
RT Journal T1 <Title>A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_jssc.2023.3339679&Exemplar=1&LAN=DE A1 Ye, Zonglin A1 Geng, Xinlin A1 Xiao, Yao A1 Xie, Qian A1 Wang, Zheng PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 0018-9200 SN 1558-173X JF IEEE Journal of Solid-State Circuits VO 59 IS 3 SP 677 OP 689 LK http://dx.doi.org/https://doi.org/10.1109/jssc.2023.3339679 DO https://doi.org/10.1109/jssc.2023.3339679 SF ELIB - SuUB Bremen
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