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1 Ergebnisse
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Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s..:
Rovinski, Austin
;
Veluri, Bandhav
;
Rao, Anuj
...
IEEE Solid-State Circuits Letters. 2 (2019) 12 - p. 289-292 , 2019
Link:
https://doi.org/10.1109/lssc.2019.2953847
RT Journal T1
Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_lssc.2019.2953847&Exemplar=1&LAN=DE A1 Rovinski, Austin A1 Veluri, Bandhav A1 Rao, Anuj A1 Ajayi, Tutu A1 Puscar, Julian A1 Dai, Steve A1 Zhao, Ritchie A1 Richmond, Dustin A1 Zhang, Zhiru A1 Galton, Ian A1 Batten, Christopher A1 Zhao, Chun A1 Taylor, Michael B. A1 Dreslinski, Ronald G. A1 Al-Hawaj, Khalid A1 Gao, Paul A1 Xie, Shaolin A1 Torng, Christopher A1 Davidson, Scott A1 Amarnath, Aporva A1 Vega, Luis PB Institute of Electrical and Electronics Engineers (IEEE) YR 2019 SN 2573-9603 JF IEEE Solid-State Circuits Letters VO 2 IS 12 SP 289 OP 292 LK http://dx.doi.org/https://doi.org/10.1109/lssc.2019.2953847 DO https://doi.org/10.1109/lssc.2019.2953847 SF ELIB - SuUB Bremen
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