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1 Ergebnisse
1
MemPool: A Scalable Manycore Architecture With a Low-Latenc..:
Riedel, Samuel
;
Cavalcante, Matheus
;
Andri, Renzo
.
IEEE Transactions on Computers. 72 (2023) 12 - p. 3561-3575 , 2023
Link:
https://doi.org/10.1109/tc.2023.3307796
RT Journal T1
MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tc.2023.3307796&Exemplar=1&LAN=DE A1 Riedel, Samuel A1 Cavalcante, Matheus A1 Andri, Renzo A1 Benini, Luca PB Institute of Electrical and Electronics Engineers (IEEE) YR 2023 SN 0018-9340 SN 1557-9956 SN 2326-3814 JF IEEE Transactions on Computers VO 72 IS 12 SP 3561 OP 3575 LK http://dx.doi.org/https://doi.org/10.1109/tc.2023.3307796 DO https://doi.org/10.1109/tc.2023.3307796 SF ELIB - SuUB Bremen
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