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HORNET: A Cycle-Level Multicore Simulator:
Pengju Ren
;
Lis, M.
;
Myong Hyon Cho
...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31 (2012) 6 - p. 890-903 , 2012
Link:
https://doi.org/10.1109/tcad.2012.2184760
RT Journal T1 <Title>HORNET: A Cycle-Level Multicore Simulator</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcad.2012.2184760&Exemplar=1&LAN=DE A1 Pengju Ren A1 Lis, M. A1 Myong Hyon Cho A1 Keun Sup Shim A1 Fletcher, C. W. A1 Khan, O. A1 Nanning Zheng A1 Devadas, S. PB Institute of Electrical and Electronics Engineers (IEEE) YR 2012 SN 0278-0070 SN 1937-4151 JF IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems VO 31 IS 6 SP 890 OP 903 LK http://dx.doi.org/https://doi.org/10.1109/tcad.2012.2184760 DO https://doi.org/10.1109/tcad.2012.2184760 SF ELIB - SuUB Bremen
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