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Hier-3D: A Methodology for Physical Hierarchy Exploration o..:
Bethur, Nesara Eranna
;
Agnesina, Anthony
;
Brunion, Moritz
...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43 (2024) 7 - p. 1957-1970 , 2024
Link:
https://doi.org/10.1109/tcad.2023.3342753
RT Journal T1 <Title>Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcad.2023.3342753&Exemplar=1&LAN=DE A1 Bethur, Nesara Eranna A1 Agnesina, Anthony A1 Brunion, Moritz A1 Garcia-Ortiz, Alberto A1 Catthoor, Francky A1 Milojevic, Dragomir A1 Komalan, Manu A1 Cavalcante, Matheus A1 Riedel, Samuel A1 Benini, Luca A1 Lim, Sung Kyu PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 0278-0070 SN 1937-4151 JF IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems VO 43 IS 7 SP 1957 OP 1970 LK http://dx.doi.org/https://doi.org/10.1109/tcad.2023.3342753 DO https://doi.org/10.1109/tcad.2023.3342753 SF ELIB - SuUB Bremen
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