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1 Ergebnisse
1
A Unified Parallel Framework for LUT Mapping and Logic Opti..:
Liu, Tianji
;
Sun, Yang
;
Chen, Lei
...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. , 2024
Link:
https://doi.org/10.1109/tcad.2024.3429079
RT Journal T1 <Title>A Unified Parallel Framework for LUT Mapping and Logic Optimization</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcad.2024.3429079&Exemplar=1&LAN=DE A1 Liu, Tianji A1 Sun, Yang A1 Chen, Lei A1 Li, Xing A1 Yuan, Mingxuan A1 Young, Evangeline F.Y. PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 0278-0070 SN 1937-4151 JF IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems SP 1 OP 1 LK http://dx.doi.org/https://doi.org/10.1109/tcad.2024.3429079 DO https://doi.org/10.1109/tcad.2024.3429079 SF ELIB - SuUB Bremen
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