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A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aide..:
Condo, Carlo
IEEE Transactions on Circuits and Systems I: Regular Papers. 69 (2022) 5 - p. 2203-2211 , 2022
Link:
https://doi.org/10.1109/tcsi.2022.3150583
RT Journal T1 <Title>A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcsi.2022.3150583&Exemplar=1&LAN=DE A1 Condo, Carlo PB Institute of Electrical and Electronics Engineers (IEEE) YR 2022 SN 1549-8328 SN 1558-0806 JF IEEE Transactions on Circuits and Systems I: Regular Papers VO 69 IS 5 SP 2203 OP 2211 LK http://dx.doi.org/https://doi.org/10.1109/tcsi.2022.3150583 DO https://doi.org/10.1109/tcsi.2022.3150583 SF ELIB - SuUB Bremen
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