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1 Ergebnisse
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The Algorithm and VLSI Architecture of High-Throughput and ..:
Tsai, Ting-Yu
;
Shen, Chung-An
;
Wu, Tsung-Lin
.
IEEE Transactions on Circuits and Systems I: Regular Papers. 71 (2024) 7 - p. 3134-3145 , 2024
Link:
https://doi.org/10.1109/tcsi.2024.3390751
RT Journal T1 <Title>The Algorithm and VLSI Architecture of High-Throughput and Highly Efficient Tensor Decomposition Engine</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcsi.2024.3390751&Exemplar=1&LAN=DE A1 Tsai, Ting-Yu A1 Shen, Chung-An A1 Wu, Tsung-Lin A1 Huang, Yuan-Hao PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 1549-8328 SN 1558-0806 JF IEEE Transactions on Circuits and Systems I: Regular Papers VO 71 IS 7 SP 3134 OP 3145 LK http://dx.doi.org/https://doi.org/10.1109/tcsi.2024.3390751 DO https://doi.org/10.1109/tcsi.2024.3390751 SF ELIB - SuUB Bremen
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