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1 Ergebnisse
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A Potential Enabler for High-Performance In-Memory Multi-Bi..:
Zhu, Haonan
;
Wu, Bi
;
Yu, Tianyang
...
IEEE Transactions on Circuits and Systems I: Regular Papers. 71 (2024) 7 - p. 3165-3178 , 2024
Link:
https://doi.org/10.1109/tcsi.2024.3395442
RT Journal T1 <Title>A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcsi.2024.3395442&Exemplar=1&LAN=DE A1 Zhu, Haonan A1 Wu, Bi A1 Yu, Tianyang A1 Chen, Ke A1 Yan, Chenggang A1 Liu, Weiqiang PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 1549-8328 SN 1558-0806 JF IEEE Transactions on Circuits and Systems I: Regular Papers VO 71 IS 7 SP 3165 OP 3178 LK http://dx.doi.org/https://doi.org/10.1109/tcsi.2024.3395442 DO https://doi.org/10.1109/tcsi.2024.3395442 SF ELIB - SuUB Bremen
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