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A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Cloc..:

Song, Yeonggeun ; Ko, Han-Gon ; Kim, Changhyun.
IEEE Transactions on Circuits and Systems II: Express Briefs.  69 (2022)  3 - p. 759-763 , 2022
Link: https://doi.org/10.1109/tcsii.2021.3123610