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1 Ergebnisse
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A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchica..:
Xiao, Kanglin
;
Cui, Xiaoxin
;
Qiao, Xin
...
IEEE Transactions on Circuits and Systems II: Express Briefs. 70 (2023) 6 - p. 1816-1820 , 2023
Link:
https://doi.org/10.1109/tcsii.2023.3234620
RT Journal T1 <Title>A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcsii.2023.3234620&Exemplar=1&LAN=DE A1 Xiao, Kanglin A1 Cui, Xiaoxin A1 Qiao, Xin A1 Song, Jiahao A1 Luo, Haoyang A1 Wang, Xin'an A1 Wang, Yuan PB Institute of Electrical and Electronics Engineers (IEEE) YR 2023 SN 1549-7747 SN 1558-3791 JF IEEE Transactions on Circuits and Systems II: Express Briefs VO 70 IS 6 SP 1816 OP 1820 LK http://dx.doi.org/https://doi.org/10.1109/tcsii.2023.3234620 DO https://doi.org/10.1109/tcsii.2023.3234620 SF ELIB - SuUB Bremen
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