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1 Ergebnisse
1
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved..:
Wang, Jiawei
;
Gao, Zhao
;
Cheng, Xu
...
IEEE Transactions on Circuits and Systems II: Express Briefs. 71 (2024) 4 - p. 1859-1863 , 2024
Link:
https://doi.org/10.1109/tcsii.2023.3335987
RT Journal T1 <Title>A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcsii.2023.3335987&Exemplar=1&LAN=DE A1 Wang, Jiawei A1 Gao, Zhao A1 Cheng, Xu A1 Wang, Jue A1 Li, Zhen A1 Han, Jun A1 Zeng, Xiaoyang PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 1549-7747 SN 1558-3791 JF IEEE Transactions on Circuits and Systems II: Express Briefs VO 71 IS 4 SP 1859 OP 1863 LK http://dx.doi.org/https://doi.org/10.1109/tcsii.2023.3335987 DO https://doi.org/10.1109/tcsii.2023.3335987 SF ELIB - SuUB Bremen
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