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1 Ergebnisse
1
Parallelized RDOQ Algorithm and Fully Pipelined Hardware Ar..:
Huang, Xiaofeng
;
Tang, Ran
;
Pan, Rui
...
IEEE Transactions on Circuits and Systems for Video Technology. 34 (2024) 7 - p. 6430-6444 , 2024
Link:
https://doi.org/10.1109/tcsvt.2023.3349278
RT Journal T1 <Title>Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tcsvt.2023.3349278&Exemplar=1&LAN=DE A1 Huang, Xiaofeng A1 Tang, Ran A1 Pan, Rui A1 Yin, Haibing A1 Wang, Zhao A1 Wang, Shiqi A1 Ma, Siwei PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 1051-8215 SN 1558-2205 JF IEEE Transactions on Circuits and Systems for Video Technology VO 34 IS 7 SP 6430 OP 6444 LK http://dx.doi.org/https://doi.org/10.1109/tcsvt.2023.3349278 DO https://doi.org/10.1109/tcsvt.2023.3349278 SF ELIB - SuUB Bremen
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