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FPGA implementation of a critical railway interlocking syst..:
Martín Nicolás, Menéndez
;
Facundo Santiago, Larosa
;
Ramiro Adrián, Ghignone
..
IEEE Latin America Transactions. 18 (2020) 2 - p. 288-294 , 2020
Link:
https://doi.org/10.1109/tla.2020.9085282
RT Journal T1
FPGA implementation of a critical railway interlocking system
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tla.2020.9085282&Exemplar=1&LAN=DE A1 Martín Nicolás, Menéndez A1 Facundo Santiago, Larosa A1 Ramiro Adrián, Ghignone A1 Nicolás, Álvarez A1 Ariel, Lutenberg PB Institute of Electrical and Electronics Engineers (IEEE) YR 2020 SN 1548-0992 JF IEEE Latin America Transactions VO 18 IS 2 SP 288 OP 294 LK http://dx.doi.org/https://doi.org/10.1109/tla.2020.9085282 DO https://doi.org/10.1109/tla.2020.9085282 SF ELIB - SuUB Bremen
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