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1 Ergebnisse
1
Design Space Exploration for 3-D Cache:
Yuh-Fang Tsai
;
Feng Wang
;
Yuan Xie
..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16 (2008) 4 - p. 444-455 , 2008
Link:
https://doi.org/10.1109/tvlsi.2007.915429
RT Journal T1
Design Space Exploration for 3-D Cache
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2007.915429&Exemplar=1&LAN=DE A1 Yuh-Fang Tsai A1 Feng Wang A1 Yuan Xie A1 Vijaykrishnan, N. A1 Irwin, M.J. PB Institute of Electrical and Electronics Engineers (IEEE) YR 2008 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 16 IS 4 SP 444 OP 455 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2007.915429 DO https://doi.org/10.1109/tvlsi.2007.915429 SF ELIB - SuUB Bremen
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