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1 Ergebnisse
1
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memo..:
Zia, Aamir
;
Jacob, Philip
;
Kim, Jin-Woo
...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18 (2010) 6 - p. 967-977 , 2010
Link:
https://doi.org/10.1109/tvlsi.2009.2017750
RT Journal T1
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2009.2017750&Exemplar=1&LAN=DE A1 Zia, Aamir A1 Jacob, Philip A1 Kim, Jin-Woo A1 Chu, Michael A1 Kraft, Russell P. A1 McDonald, John F. PB Institute of Electrical and Electronics Engineers (IEEE) YR 2010 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 18 IS 6 SP 967 OP 977 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2009.2017750 DO https://doi.org/10.1109/tvlsi.2009.2017750 SF ELIB - SuUB Bremen
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