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1 Ergebnisse
1
Design and Optimization of Power-Gated Circuits With Autono..:
Seomun, Jun
;
Shin, Youngsoo
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19 (2011) 2 - p. 227-236 , 2011
Link:
https://doi.org/10.1109/tvlsi.2009.2033356
RT Journal T1 <Title>Design and Optimization of Power-Gated Circuits With Autonomous Data Retention</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2009.2033356&Exemplar=1&LAN=DE A1 Seomun, Jun A1 Shin, Youngsoo PB Institute of Electrical and Electronics Engineers (IEEE) YR 2011 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 19 IS 2 SP 227 OP 236 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2009.2033356 DO https://doi.org/10.1109/tvlsi.2009.2033356 SF ELIB - SuUB Bremen
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