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1 Ergebnisse
1
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s ..:
Hoya, Katsuhiko
;
Takashima, Daisaburo
;
Shiratake, Shinichiro
...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18 (2010) 12 - p. 1745-1752 , 2010
Link:
https://doi.org/10.1109/tvlsi.2009.2034380
RT Journal T1
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2009.2034380&Exemplar=1&LAN=DE A1 Hoya, Katsuhiko A1 Takashima, Daisaburo A1 Shiratake, Shinichiro A1 Ogiwara, Ryu A1 Miyakawa, Tadashi A1 Shiga, Hidehiro A1 Doumae, Sumiko M. A1 Ohtsuki, Sumito A1 Kumura, Yoshinori A1 Shuto, Susumu A1 Ozaki, Tohru A1 Yamakawa, Koji A1 Kunishima, Iwao A1 Nitayama, Akihiro A1 Fujii, Shuso PB Institute of Electrical and Electronics Engineers (IEEE) YR 2010 SN 1063-8210 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 18 IS 12 SP 1745 OP 1752 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2009.2034380 DO https://doi.org/10.1109/tvlsi.2009.2034380 SF ELIB - SuUB Bremen
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