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1 Ergebnisse
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Parallel Architecture for Hierarchical Optical Flow Estimat..:
Barranco, Francisco
;
Tomasi, Matteo
;
Diaz, Javier
..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20 (2012) 6 - p. 1058-1067 , 2012
Link:
https://doi.org/10.1109/tvlsi.2011.2145423
RT Journal T1 <Title>Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2011.2145423&Exemplar=1&LAN=DE A1 Barranco, Francisco A1 Tomasi, Matteo A1 Diaz, Javier A1 Vanegas, Mauricio A1 Ros, Eduardo PB Institute of Electrical and Electronics Engineers (IEEE) YR 2012 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 20 IS 6 SP 1058 OP 1067 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2011.2145423 DO https://doi.org/10.1109/tvlsi.2011.2145423 SF ELIB - SuUB Bremen
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