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1 Ergebnisse
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A Fast-Acquisition All-Digital Delay-Locked Loop Using a St..:
Ho, Yung-Hsiang
;
Yao, Chia-Yu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24 (2016) 2 - p. 759-763 , 2016
Link:
https://doi.org/10.1109/tvlsi.2015.2407577
RT Journal T1
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2015.2407577&Exemplar=1&LAN=DE A1 Ho, Yung-Hsiang A1 Yao, Chia-Yu PB Institute of Electrical and Electronics Engineers (IEEE) YR 2016 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 24 IS 2 SP 759 OP 763 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2015.2407577 DO https://doi.org/10.1109/tvlsi.2015.2407577 SF ELIB - SuUB Bremen
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