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74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using ..:

Wang, Chua-Chin ; Lou, Pang-Yen ; Tsai, Tsung-Yi.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  27 (2019)  10 - p. 2464-2468 , 2019
Link: https://doi.org/10.1109/tvlsi.2019.2925574