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1 Ergebnisse
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Architecture, Chip, and Package Codesign Flow for Interpose..:
Kim, Jinwoo
;
Murali, Gauthaman
;
Park, Heechun
...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28 (2020) 11 - p. 2424-2437 , 2020
Link:
https://doi.org/10.1109/tvlsi.2020.3015494
RT Journal T1 <Title>Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2020.3015494&Exemplar=1&LAN=DE A1 Kim, Jinwoo A1 Murali, Gauthaman A1 Park, Heechun A1 Qin, Eric A1 Kwon, Hyoukjun A1 Chekuri, Venkata Chaitanya Krishna A1 Rahman, Nael Mizanur A1 Dasari, Nihar A1 Singh, Arvind A1 Lee, Minah A1 Torun, Hakki Mert A1 Roy, Kallol A1 Swaminathan, Madhavan A1 Mukhopadhyay, Saibal A1 Krishna, Tushar A1 Lim, Sung Kyu PB Institute of Electrical and Electronics Engineers (IEEE) YR 2020 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 28 IS 11 SP 2424 OP 2437 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2020.3015494 DO https://doi.org/10.1109/tvlsi.2020.3015494 SF ELIB - SuUB Bremen
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