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A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With ..:

Lan, Yi-Hao ; Liu, Shen-Iuan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  32 (2024)  4 - p. 704-713 , 2024
Link: https://doi.org/10.1109/tvlsi.2023.3330012