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1 Ergebnisse
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Layer-Sensitive Neural Processing Architecture for Error-To..:
Li, Zeju
;
Wang, Qinfan
;
Zou, Zihan
...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 32 (2024) 5 - p. 797-809 , 2024
Link:
https://doi.org/10.1109/tvlsi.2024.3369648
RT Journal T1 <Title>Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2024.3369648&Exemplar=1&LAN=DE A1 Li, Zeju A1 Wang, Qinfan A1 Zou, Zihan A1 Shen, Qiao A1 Xie, Na A1 Cai, Hao A1 Zhang, Hao A1 Liu, Bo PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 32 IS 5 SP 797 OP 809 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2024.3369648 DO https://doi.org/10.1109/tvlsi.2024.3369648 SF ELIB - SuUB Bremen
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