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1 Ergebnisse
1
iEDCL: Streamlined, False-Error-Free Error Detection and Co..:
Yu, Runze
;
Li, Zhenhao
;
Deng, Xi
...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 32 (2024) 8 - p. 1436-1446 , 2024
Link:
https://doi.org/10.1109/tvlsi.2024.3409315
RT Journal T1 <Title>iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2024.3409315&Exemplar=1&LAN=DE A1 Yu, Runze A1 Li, Zhenhao A1 Deng, Xi A1 Wang, Zhaoxu A1 Jia, Wei A1 Zhang, Haoming A1 Liu, Zhenglin PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 32 IS 8 SP 1436 OP 1446 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2024.3409315 DO https://doi.org/10.1109/tvlsi.2024.3409315 SF ELIB - SuUB Bremen
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