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1 Ergebnisse
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A Design Framework for Generating Energy-Efficient Accelera..:
Zhou, Zikang
;
Duan, Xuyang
;
Han, Jun
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 32 (2024) 8 - p. 1485-1497 , 2024
Link:
https://doi.org/10.1109/tvlsi.2024.3409649
RT Journal T1 <Title>A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2024.3409649&Exemplar=1&LAN=DE A1 Zhou, Zikang A1 Duan, Xuyang A1 Han, Jun PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems VO 32 IS 8 SP 1485 OP 1497 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2024.3409649 DO https://doi.org/10.1109/tvlsi.2024.3409649 SF ELIB - SuUB Bremen
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