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1 Ergebnisse
1
Toward Efficient Asynchronous Circuits Design Flow Using Ba..:
Zhou, Lingfeng
;
Xiao, Shanlin
;
Wang, Huiyao
...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. , 2024
Link:
https://doi.org/10.1109/tvlsi.2024.3418769
RT Journal T1
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint
UL https://suche.suub.uni-bremen.de/peid=cr-10.1109_tvlsi.2024.3418769&Exemplar=1&LAN=DE A1 Zhou, Lingfeng A1 Xiao, Shanlin A1 Wang, Huiyao A1 Wang, Jinghai A1 Xu, Zeyang A1 Wang, Bohan A1 Yu, Zhiyi PB Institute of Electrical and Electronics Engineers (IEEE) YR 2024 SN 1063-8210 SN 1557-9999 JF IEEE Transactions on Very Large Scale Integration (VLSI) Systems SP 1 OP 12 LK http://dx.doi.org/https://doi.org/10.1109/tvlsi.2024.3418769 DO https://doi.org/10.1109/tvlsi.2024.3418769 SF ELIB - SuUB Bremen
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