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Design of Synthesis-time Vectorized Arithmetic Hardware for..:
Bommana, Ashish Reddy
;
Siddamshetty, Susheel Ujwal
;
Pudi, Dhilleswararao
...
ACM Transactions on Design Automation of Electronic Systems. 28 (2023) 3 - p. 1-35 , 2023
Link:
https://doi.org/10.1145/3567423
RT Journal T1 <Title>Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1145_3567423&Exemplar=1&LAN=DE A1 Bommana, Ashish Reddy A1 Siddamshetty, Susheel Ujwal A1 Pudi, Dhilleswararao A1 Thumatti K. R., Arvind A1 Boppu, Srinivas A1 Sabarimalai Manikandan, M A1 Cenkeramaddi, Linga Reddy PB Association for Computing Machinery (ACM) YR 2023 SN 1084-4309 SN 1557-7309 JF ACM Transactions on Design Automation of Electronic Systems VO 28 IS 3 SP 1 OP 35 LK http://dx.doi.org/https://doi.org/10.1145/3567423 DO https://doi.org/10.1145/3567423 SF ELIB - SuUB Bremen
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