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UST/DME: a clock tree router for general skew constraints:
Tsao, Chung-wen Albert
;
Koh, Cheng-kok
ACM Transactions on Design Automation of Electronic Systems. 7 (2002) 3 - p. 359-379 , 2002
Link:
https://doi.org/10.1145/567270.567271
RT Journal T1 <Title>UST/DME: a clock tree router for general skew constraints</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1145_567270.567271&Exemplar=1&LAN=DE A1 Tsao, Chung-wen Albert A1 Koh, Cheng-kok PB Association for Computing Machinery (ACM) YR 2002 SN 1084-4309 SN 1557-7309 JF ACM Transactions on Design Automation of Electronic Systems VO 7 IS 3 SP 359 OP 379 LK http://dx.doi.org/https://doi.org/10.1145/567270.567271 DO https://doi.org/10.1145/567270.567271 SF ELIB - SuUB Bremen
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