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A system verilog approach for verification of memory contro..:
K B, Sowmya
;
P, Gagana
International Journal of Reconfigurable and Embedded Systems (IJRES). 9 (2020) 2 - p. 153 , 2020
Link:
https://doi.org/10.11591/ijres.v9.i2.pp153-157
RT Journal T1 <Title>A system verilog approach for verification of memory controller</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.11591_ijres.v9.i2.pp153-157&Exemplar=1&LAN=DE A1 K B, Sowmya A1 P, Gagana PB Institute of Advanced Engineering and Science YR 2020 SN 2722-2608 SN 2089-4864 JF International Journal of Reconfigurable and Embedded Systems (IJRES) VO 9 IS 2 SP 153 LK http://dx.doi.org/https://doi.org/10.11591/ijres.v9.i2.pp153-157 DO https://doi.org/10.11591/ijres.v9.i2.pp153-157 SF ELIB - SuUB Bremen
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