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Control-theoretic adaptive cache-fair scheduling of chip mu..:
Arslan, Huseyin G
;
Tian, Yu-Chu
;
Li, Fenglian
..
Transactions of the Institute of Measurement and Control. 40 (2017) 10 - p. 3095-3104 , 2017
Link:
https://doi.org/10.1177/0142331217715064
RT Journal T1 <Title>Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1177_0142331217715064&Exemplar=1&LAN=DE A1 Arslan, Huseyin G A1 Tian, Yu-Chu A1 Li, Fenglian A1 Peng, Chen A1 Fei, Min-Rui PB SAGE Publications YR 2017 SN 0142-3312 SN 1477-0369 JF Transactions of the Institute of Measurement and Control VO 40 IS 10 SP 3095 OP 3104 LK http://dx.doi.org/https://doi.org/10.1177/0142331217715064 DO https://doi.org/10.1177/0142331217715064 SF ELIB - SuUB Bremen
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