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Optimization of CMOS power-cell layout for improving juncti..:
Lee, Ockgoo
;
Han, Jeonghu
;
An, Kyu Hwan
...
IEICE Electronics Express. 11 (2014) 19 - p. 20140523-20140523 , 2014
Link:
https://doi.org/10.1587/elex.11.20140523
RT Journal T1 <Title>Optimization of CMOS power-cell layout for improving junction breakdown</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1587_elex.11.20140523&Exemplar=1&LAN=DE A1 Lee, Ockgoo A1 Han, Jeonghu A1 An, Kyu Hwan A1 Kim, Hyoungsoo A1 Hur, Joonhui A1 Yang, Kiseok A1 Lim, Kyutae A1 Lee, Chang-Ho A1 Laskar, Joy PB Institute of Electronics, Information and Communications Engineers (IEICE) YR 2014 SN 1349-2543 JF IEICE Electronics Express VO 11 IS 19 SP 20140523 OP 20140523 LK http://dx.doi.org/https://doi.org/10.1587/elex.11.20140523 DO https://doi.org/10.1587/elex.11.20140523 SF ELIB - SuUB Bremen
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