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1 Ergebnisse
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A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Vo..:
HAYASHIKOSHI, Masanori
;
TANIZAKI, Hiroaki
;
MURAI, Yasumitsu
...
IEICE Transactions on Electronics. E102.C (2019) 4 - p. 287-295 , 2019
Link:
https://doi.org/10.1587/transele.2018cdp0007
RT Journal T1
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications
UL https://suche.suub.uni-bremen.de/peid=cr-10.1587_transele.2018cdp0007&Exemplar=1&LAN=DE A1 HAYASHIKOSHI, Masanori A1 TANIZAKI, Hiroaki A1 MURAI, Yasumitsu A1 TSUJI, Takaharu A1 KAWABATA, Kiyoshi A1 NII, Koji A1 NODA, Hideyuki A1 KONDO, Hiroyuki A1 MATSUDA, Yoshio A1 HIDAKA, Hideto PB Institute of Electronics, Information and Communications Engineers (IEICE) YR 2019 SN 0916-8524 SN 1745-1353 JF IEICE Transactions on Electronics VO E102.C IS 4 SP 287 OP 295 LK http://dx.doi.org/https://doi.org/10.1587/transele.2018cdp0007 DO https://doi.org/10.1587/transele.2018cdp0007 SF ELIB - SuUB Bremen
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