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Low-Power Design Methodology of Voltage Over-Scalable Circu..:
MASUDA, Yutaka
;
NAGAYAMA, Jun
;
CHENG, TaiYu
...
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E105.A (2022) 3 - p. 509-517 , 2022
Link:
https://doi.org/10.1587/transfun.2021vlp0002
RT Journal T1 <Title>Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1587_transfun.2021vlp0002&Exemplar=1&LAN=DE A1 MASUDA, Yutaka A1 NAGAYAMA, Jun A1 CHENG, TaiYu A1 ISHIHARA, Tohru A1 MOMIYAMA, Yoichi A1 HASHIMOTO, Masanori PB Institute of Electronics, Information and Communications Engineers (IEICE) YR 2022 SN 0916-8508 SN 1745-1337 JF IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences VO E105.A IS 3 SP 509 OP 517 LK http://dx.doi.org/https://doi.org/10.1587/transfun.2021vlp0002 DO https://doi.org/10.1587/transfun.2021vlp0002 SF ELIB - SuUB Bremen
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