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Placement with Symmetry Constraints for Analog IC Layout De..:
HIRAKAWA, Natsumi
;
FUJIYOSHI, Kunihiro
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A (2009) 2 - p. 467-474 , 2009
Link:
https://doi.org/10.1587/transfun.e92.a.467
RT Journal T1 <Title>Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation</Title> UL https://suche.suub.uni-bremen.de/peid=cr-10.1587_transfun.e92.a.467&Exemplar=1&LAN=DE A1 HIRAKAWA, Natsumi A1 FUJIYOSHI, Kunihiro PB Institute of Electronics, Information and Communications Engineers (IEICE) YR 2009 SN 0916-8508 SN 1745-1337 JF IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences VO E92-A IS 2 SP 467 OP 474 LK http://dx.doi.org/https://doi.org/10.1587/transfun.e92.a.467 DO https://doi.org/10.1587/transfun.e92.a.467 SF ELIB - SuUB Bremen
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